The present invention relates generally to a non-volatile semiconductor memory device. More particularly, the present invention relates to a non-volatile semiconductor memory device which makes it possible to store four-value information (two-bit information) in one memory cell and increases a memory capacity. The present invention relates to a technology which will be useful when applied to an electrically rewritable non-volatile semiconductor memory device such as a flash memory. A conventional non-volatile semiconductor memory device capable of storing information by injecting an electron into a floating gate, such as a flash memory, is described, for example, in xe2x80x9c1994 Symposium on VLSI Circuits Digest of Technical Papersxe2x80x9d, pp. 61-62. Each of the (1) erase, (2) write, (3) write verify and (4) read operations of this conventional flash memory will be explained.
FIG. 35 of the accompanying drawings shows a principal circuit portion of memory cells MC connected to a word line WL and a bit line EL so as to explain the operations of a flash memory for storing two-value information (one-bit information) in one memory cell. Reference numerals N9 to 112 denote NMOS transistors for executing a switch operation (hereinafter merely called the xe2x80x9cNMOS switchxe2x80x9d). A source line is represented by symbol SOL.
The state where electrons are injected to the floating gate of the memory cell MC and the threshold voltage of this memory cell MC (Vth0) is high will be assumed as the erase state, that is, the state where the written information is xe2x80x9c0xe2x80x9d. On the contrary, the state where the electron is not injected into the floating gate and the threshold voltage of the memory cell MC is low (Vth1) will be assumed as a written state, that is, the state where the written information is xe2x80x9c1xe2x80x9d.
FIG. 36 typically shows a threshold voltage distribution of the memory cell when the memory cell latches the two-value information in this way.
(1) Erase Operation:
In this example, the erase operation is made for each word line. The erase operation is carried out by setting the word line WL to 12 V, for example, and applying xe2x88x924 V, for example, to a substrate voltage VWEL of the memory cell MC and a source line SOL. In consequence, the electron are injected to the floating gate, the threshold voltage of the memory cell MC becomes high, and the erase state is established.
(2) Write Operation:
The write operation is the one that extracts the electrons in the floating gate and lowers the threshold voltage of the memory cell.
First, an input/output line IO is set to a high level (called also xe2x80x9cHighxe2x80x9d) when write is made to the memory cell MC and to a low level (called also xe2x80x9cLowxe2x80x9d) when write is not made, and a sense latch SL is caused to latch the data of the xe2x80x9cHighxe2x80x9d or xe2x80x9cLowxe2x80x9d level.
Next, the operation power source voltage VSA of the sense latch SL is raised to 4 V, for example, from the power supply voltage VCC to turn ON the NMOS switch N10. If xe2x80x9cHighxe2x80x9d is latched by the sense latch SL at this time, the node side A of the sense latch SL is xe2x80x9cHighxe2x80x9d, so that the NMOS switch N11 is turned ON and the bit line EL is precharged to 4 V through the NMOS switches N10 and N11. If xe2x80x9cLowxe2x80x9d is latched by the sense latch SL, on the other hand, the node A is xe2x80x9cLowxe2x80x9d, so that the NMOS switch N11 is OFF and the bit line EL is not precharged and falls to 0 V. Thereafter, the voltage of a control signal line PG is lowered to turn OFF the NMOS switch N10, and the control signal line TR is then raised to turn ON the NMOS switch N12. The word line WL is set to xe2x88x929 V, for example, and the write operation is carried out. At this time, the source line and the substrate voltage VWEL of the memory cell MC are kept at 0 V. The voltage of the control signal line TR is then lowered to turn OFF the NMOS switch N10 to set the word line W to 0 V, the control signal line DDC is raised to turn ON the NMOS switch N9 and to discharge the bit line BL. The voltage of the control signal line DDC is lowered to turn OFF the NMOS switch N9, and the next write verify operation is carried out.
(3) Write Verify Operation:
In the write verify operation, the voltage VSA is first set to 1 V, for example, to raise the control signal line PG and turn ON the NMOS switch N10. As described in the (2) write operation, if xe2x80x9cHighxe2x80x9d is latched in the sense latch SL, the NMOS switch N11 is turned ON, and the bit line BL is precharged to 1 V. If xe2x80x9cLowxe2x80x9d is latched, the NMOS switch N11 is turned OFF, so that the bit line EL is not precharged. Next, the voltage of the control signal line PG Is lowered to turn OFF the NMOS switch N10. If the word line WL is 1.5 V, and the source line and the substrate voltage VWEL of the memory cell MC are 0 V, for example, the memory cell MC is turned ON if its threshold voltage is low, a current flows from the bit line EL to the source line side and hence, the potential of the bit line EL drops, due to the (2) write operation. If the threshold voltage of the memory cell MC is not under the low state by the (2) write operation, on the other hand, the memory cell MC is not turned ON and the potential of the bit line EL does not drop.
After the voltage of the word line is returned to 0 V, the control signal line TR is raised to turn ON the NMOS switch N12, If the potential of the bit line BL lowers at this time, the potential of the node A lowers, too, and xe2x80x9cHighxe2x80x9d latched by the sense latch SL inverts to xe2x80x9cLowxe2x80x9d. If the potential of the bit line EL does not lower, however, the potential of the node A does not lower and xe2x80x9cHighxe2x80x9d latched by the sense latch SL remains xe2x80x9cHighxe2x80x9d and does not lower.
When the (2) write operation is made to the memory cell MC and the threshold voltage of the memory cell MC lowers (the state where xe2x80x9c1xe2x80x9d is written), xe2x80x9cHighxe2x80x9d latched by the sense latch SL inverts to xe2x80x9cLowxe2x80x9d due to 10 the write verify operation and the write operation is judged as being finished. In contrast, when the threshold voltage of the memory cell MC remains high due to the (2) write operation (the state where xe2x80x9c0xe2x80x9d is written), the operations (2) and (3) are repeated until the sense latch SL inverts from xe2x80x9cHighxe2x80x9d to xe2x80x9cLowxe2x80x9d.
(4) Read Operation:
First, the control signal line DDC is raised to turn ON the NMOS switch N9 and the bit line EL is discharged. Next, the voltage VSA is set to 1 V, for example, to raise the control signal line SET and to turn ON the NMOS switch N13. The node side A of the sense latch circuit SL is set to 1 V and the control signal line TR is raised. The NMOS switch N12 is turned ON and the bit line EL is precharged to 1 V. The voltage of the control signal line TR is lowered, the NMOS switch N12 is turned OFF, the voltage of the SET line is lowered and the NMOS switch N13 is turned OFF. The substrate voltage VWEL and the voltage of the source line are then set to 0 V, for example, and the word line WL is set to the power supply voltage VCC. When the threshold voltage of the memory cell MC is low, the memory cell MC is turned ON, a current flows from the bit line BL to the source line side and the potential of the bit line BL drops. When the threshold voltage of the memory cell MC is high, the memory cell MC is not turned ON and the potential of the bit line BL does not drop. Next, after the voltage of the word line WL is set to 0 V, the control signal line TR is raised and the NMOS switch N12 is turned ON. If the memory cell MC is turned ON, the potential of the bit line BL is low. Therefore, the potential of the node A is low, too. If the memory cell MC is not turned ON, on the other hand, the potential of the bit line BL does not drop, and the potential of the node A does not drop, either. In this way, the information stored in the memory cell MC, that is, the information corresponding to the case where the threshold voltage is low (the state where xe2x80x9c1xe2x80x9d is written) and the case where it is high (the state where xe2x80x9c0xe2x80x9d is written), is read out.
A greater memory capacity and a smaller area have been desired for non-volatile semiconductor memory devices. As described above, however, when only one-bit information can be stored in one memory cell, the number of memory cell arrays must be increased to achieve a greater capacity. For this reason, in order to achieve a greater capacity in the non-volatile semiconductor memory devices, the chip area must be inevitably increased irrespective of the progress of the micro fabrication technology in the technical field of the semiconductor integrated circuits.
The present invention is directed to make it possible to store four-value information (two-bit information) in one memory cell.
Another object of the present invention is to increase a capacity of a non-volatile semiconductor memory cell and to reduce the increase of a chip area with the increase of the capacity.
These and other objects and novel features of the present invention will become more apparent from the following detailed description of the invention in conjunction with the accompanying drawings.
Among the inventions disclosed in this application, the following will briefly illustrate some typical inventions.
In the verify operation, in brief, the write operation is effected by serially applying three different kinds of voltages to the word line so as to control the threshold voltage of the memory cell, the two-value (one-bit) write data corresponding to the four-value (two-bit) information to to be written are synthesized by a write data conversion circuit (1) for each of the write operations carried out three times, and the four-value (two-bit) information is written to one memory cell. To read the stored information, three different kinds of voltages are applied to the word line, the three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit (2) and the stored information of the memory cell is converted to two-bit information.
More particularly, when the data of an electrically erasable and writable non-volatile memory cell (MC) is rewritten, a non-volatile semiconductor memory device for controlling the non-volatile memory cell (MC) to an erase state, a first write state, a second write state or a third write state each having a different threshold voltage and making it possible for one memory cell to store four-value information, includes write control means (12) for controlling each of the first write operation (xe2x80x9cwrite 1xe2x80x9d) for the non-volatile memory cell to the erase state and selectively non-volatile memory cell under the erase state to the first write state, the second write operation (xe2x80x9cwrite 2xe2x80x9d) for selectively setting the non-volatile memory cell to the second write state after the first write operation and the third write operation (xe2x80x9cwrite 3xe2x80x9d) for selectively setting the non-volatile memory cell to the third write state after the second write operation, and a write data conversion circuit (1) for generating one-bit write information deciding whether or not the non-volatile memory cell is set to the first write state by the first write operation, one-bit write information deciding whether or not the non-volatile memory cell is set to the second write state by the second write operation and one-bit write information deciding whether or not the non-volatile memory cell is set to the third write state by the third write operation, from two-bit write data given from outside. The memory device includes further data latch means (sense latch SL) for latching the write information so generated by the write data conversion circuit as to correspond to each of the first to third write operations, for each of these first to third write operations, and for selecting whether or not the memory cell is set to the corresponding write state for each of the first to third write operations.
When the memory cell is connected to the bit line and has a sense latch whose memory node is connected to the bit line and a switch device for selectively connecting the bit line to an input/output line, the data latch means described above can be constituted to a sense latch (SL) which is connected to the bit line selected by the switch device.
When the threshold voltage of the non-volatile memory cell under the erase state, the first write state, the second write state and the third write state are Vth0, Vth1, Vth2 and Vth3 from the higher side, respectively, the write verify voltages Vv1, Vv2 and Vv3 in the first to so set as to satisfy the relation Vth1 less than Vv1 less than Vth0, Vth2 less than Vv2 less than Vt1 and Vth3 less than Vv3 c Vth2.
When the erase state, the first write state, the second write state and the third write state of the non-volatile memory cell are assumed to correspond to xe2x80x9c00xe2x80x9d, xe2x80x9c00xe2x80x9d, xe2x80x9c10xe2x80x9d and xe2x80x9c11xe2x80x9d of the two-bit write data, for example, the write data conversion circuit sets the write information in each of the first to third write operations to a write non-select level (xe2x80x9c0xe2x80x9d) in accordance with the first state (xe2x80x9c00xe2x80x9d) of the two-bit write data, sets the write information in the first write operation to a write select level (xe2x80x9c1xe2x80x9d) and the write information in each of the second and third write operations to the write non-select level (xe2x80x9c01xe2x80x9d) in accordance with the second state (xe2x80x9c01xe2x80x9d) of the two-bit write data, sets the write information in each of the first and second write operations to the write select level (xe2x80x9c1xe2x80x9d) and the write information in the third write operation to the non-select level (xe2x80x9c0xe2x80x9d) in accordance with the third state of the two-bit write data, and sets the write information in each of the fist to third write operations to the write select level (xe2x80x9c1xe2x80x9d) in accordance with the fourth state of the two-bit write information.
In this way, the threshold voltages of the memory cell are controlled by dividing the write verify voltage into three kinds and dividedly conducting the write operations, and the two-value (one-bit) write data are generated in such a manner as to correspond to the write four-value (two-bit) information in each of the write operations carried out thrice. Accordingly, the four-value (two-bit) information can be written into one memory cell. In other words, the memory capacity of the non-volatile memory cell can be doubled.
In order to make it possible to read the four-value (two-bit) information stored in the way described above to the outside as the two-value (one-bit) information, the non-volatile semiconductor memory device includes a read control means (12) for controlling each of the first read operation for selecting the memory cell in accordance with a word line select level between the threshold voltage of the non-volatile memory cell under the erase state and the threshold voltage under the first write state, the second read operation for selecting the memory cell in accordance with the word line select level between the threshold voltage of the non-volatile memory cell under the first write state and the threshold voltage under the second write state, and the third read operation for selecting the memory cell in accordance with the world line select level between the threshold voltage of the non-volatile memory cell under the second write state and the threshold voltage under the third write state, and a read data conversion circuit (2) for generating two-bit read data representing to which of the erase state, the first write state, the second write stage and the third write state the state of the memory cell as the read object corresponds, from the one-bit information obtained by each of the first to third read operations by the read control means.
When the threshold voltages of the non-voltage memory under the erase state, the first write state, the second write state and the third write state are Vth0, Vth1, Vth2 and Vth3 from the higher side, the word line select levels Vr1, Vr2 and Vr3 in the first to third read operations can be so set as to satisfy the relation Vth1 less than Vr1 less than Vth0, Vth2 less than Vr2 c Vth1 and Vth3 less than Vr3 less than Vth2.
Assuming that the erase state, the first write state, the second write state and the third write state of the non-volatile memory cells correspond to the states of the two-bit write data xe2x80x9c00xe2x80x9d, xe2x80x9c01xe2x80x9d, xe2x80x9c10xe2x80x9d and xe2x80x9c11xe2x80x9d, respectively, the read data conversion circuit outputs the two-bit read data as the first state (xe2x80x9c00xe2x80x9d) when the three-bit information obtained by the first to third read operations all have the first logic value (xe2x80x9c0xe2x80x9d), outputs the two-bit read data as the second state (xe2x80x9c01xe2x80x9d) when the one-bit information obtained by the first read operation has the second logic value (xe2x80x9c1xe2x80x9d) while the two-bit information obtained by the second and third read operations all have the first logic value (xe2x80x9c01xe2x80x9d), outputs the two-bit read data as the third state (xe2x80x9c10xe2x80x9d) when the two-bit information obtained by the first and second read operations have the second logic value (xe2x80x9c1xe2x80x9d) while the two-bit information obtained by the third read operation has the first logic value (xe2x80x9c0xe2x80x9d), and outputs the two-bit read data as the fourth state (xe2x80x9c11xe2x80x9d) when the two-bit information obtained by the first to third read operations all have the second long value (xe2x80x9c1xe2x80x9d).
When three kinds of voltages are set as the word line select level to be applied to the word line in the read operation and the two-value (one-bit) data read out from the memory cell by the read operations carried out three times are applied to the read data conversion circuit 2 as described above, the read conversion circuit can convert the memory information of the memory cell to a two-bit data string and can output this data string.
As will be later described in detail with reference to FIGS. 10 and 11, after the operation which applies a write pulse for giving a voltage for taking the charge into and out from the memory cell to each memory cell is made, a voltage is applied to the control gate so as to judge whether or not the memory cell has a required threshold voltage, and this judgment is made on the basis of the value of a current flowing through the memory cell at this time. These operations constitute a cycle, and when this cycle is repeated a plurality of times, the width of the write pulse or the absolute value of the pulse voltage is preferably increased. If such operations are conducted at the same write pulse, it becomes more difficult to take the charge into and out from the memory cell as the cycle is repeated, but the means described above can particularly improve the write operation speed.
Preferably, the threshold voltages are set so that among a plurality of threshold voltages that can be set to one memory cell ni such a manner as to correspond to a plurality of bit information, the threshold voltages are preferably set so that the Hamming distance between the information corresponding to the adjacent threshold voltages becomes minimal.
If a plurality of bit information are two bits in this case, for example, the corresponding information may be sit to xe2x80x9c00xe2x80x9d, xe2x80x9c01xe2x80x9d, xe2x80x9c11xe2x80x9d and xe2x80x9c10xe2x80x9d from the lowest side or the highest side of the four threshold voltages that can be so set to one memory cell as to correspond to the two-bit information. According to such a definition of the bit information, any error of data due to the change of the threshold voltage remains the en-or of one bit at most, and subsequent data correction becomes easier. In other words, if any data error exists, xe2x80x9c11xe2x80x9d changes to the data xe2x80x9c01xe2x80x9d or xe2x80x9c10xe2x80x9d. Therefore, the error can be collected to a correct data by correcting only one bit.
The threshold voltage of the memory cell after the irradiation of ultra-violet rays or the threshold voltage under a thermal equilibrium state can be set to a voltage in the proximity of the lowest or highest threshold voltage among the four threshold voltages that can be set. The threshold voltage is likely to change to the threshold voltage under the thermal equilibrium state. Therefore, when the threshold voltage under the thermal equilibrium state is set to a voltage near the lowest threshold voltage, the data can be written at a high speed. When it is set to a voltage near the highest threshold voltage, the data can be erased at a high speed. As will be explained later with reference to FIGS. 6 to 9, the number of times of the data write operations is greater. Therefore, when the threshold voltage under the thermal equilibrium state is set to the voltage near the low set threshold voltage, throughput of the apparatus can be presumably improved.
In another embodiment of the present invention, the threshold voltage Vth under the thermal equilibrium state is set near the center of the distribution of the threshold voltage. Assuming that the threshold voltages are V1, V2, V3 and V4, the threshold voltage under the thermal equilibrium state is set between V2 and V3. According to this method, the potential differences are small between V1 and Vth and between V4 and Vth. Therefore, the threshold voltage is difficult to change. Further preferably, the threshold voltage under the thermal equilibrium state is set between the threshold voltages providing the greatest Hamming distance between the information corresponding to the threshold voltages. For example, when xe2x80x9c00xe2x80x9d, xe2x80x9c01xe2x80x9d, xe2x80x9c10xe2x80x9d and xe2x80x9c11xe2x80x9d correspond to the threshold voltages from the higher side or the lower side, the threshold voltage of the memory cell after the irradiation of the ultra-violet rays may be set between xe2x80x9c01xe2x80x9d and xe2x80x9c10xe2x80x9d. In other words, since the thermal equilibrium state exists between the threshold voltages corresponding to xe2x80x9c01xe2x80x9d and xe2x80x9c10xe2x80x9d, it may be interpreted that the transition of the data does not occur between xe2x80x9c01xe2x80x9d and xe2x80x9c10xe2x80x9d.